-------------------------------------------------------------------------------
--
-- Title       : test2
-- Design      : test2
-- Author      : aldec
-- Company     : Microsoft
--
-------------------------------------------------------------------------------
--
-- File        : C:\Users\vincenti\Desktop\testworkspace\wkspace\test2\src\test2.vhd
-- Generated   : Tue Feb 10 14:09:00 2015
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {test2} architecture {test2}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity test2 is
	port(
		alpha : in std_logic;
		beta : in std_logic;
		zeta : out std_logic;
		clk: in std_logic;   
		reset: in std_logic; 
		din: in std_logic;   
		dout: out std_logic 
		);
end test2;


architecture test2 of test2 is
begin
	
	combinational: process( alpha, beta)
	begin  
		zeta <= alpha xnor beta;
	end process;
	
--	dflipflop process
	dff1: process (clk, reset)
	begin
		if reset='1' then	--asynchronous reset active high
			dout <= '0';
		elsif (clk'event and clk='1') then  --clk rising edge
			dout <= din;
		end if;
	end process;
	
	
end test2;
